1. Field of the Invention
The present invention relates to a semiconductor memory apparatus which can make a read speed of a memory cell faster. Especially, the present invention relates to a semiconductor memory apparatus which can make a read speed of a memory cell faster by using a sense amplifier having an input signal generator for generating an input signal to a differential amplifier circuit and a current detector for detecting a current flowing through a memory cell, in an ON/OFF judgment of a memory cell voltage.
2. Description of the Related Art
In a conventional sense amplifier, a circuit for reading out a main memory cell is designed such that an output terminal of a current detector to which the main memory cell is connected is connected to one input terminal of a differential amplifier circuit and an output terminal of a reference current detector to which a reference cell is connected is connected to the other input terminal of the differential amplifier circuit.
In the conventional read circuit, as shown in FIGS. 1 and 2, an output signal VSi (i=1, 2, . . . , n) of a main memory cell current detector connected to a main memory cell Mi (i=1, 2, . . . , n) is inputted to one input terminal of the differential amplifier circuit, and an output signal VR of a reference current detector connected to the reference cell is inputted to the other input terminal of the differential amplifier circuit.
In the current detectors, in order to detect micro currents flowing through the main memory cell and the reference cell, resistances of resistors Ri (i=1, 2, . . . , n) and RR1 and RR2 are set to be large to then obtain a margin for differential input signals inputted to the differential amplifier circuit when the reading-out operation is done.
Thus, parasitic capacities Ci (i=1, 2, . . . , n) and CR existing on input signal lines of the differential amplifier circuit are viewed as being large. Hence, there are limitations on reductions of times until the signals VSi (i=1, 2, . . . , n) and VR reach desired voltages, respectively. In addition, since the parasitic capacity CR is greater than the parasitic capacity Ci, as shown in FIG. 2, an actual rise of a reference voltage VRR becomes slower than a rise of an ideal reference voltage VRI (similar to an approximately average of an ON cell voltage VSON and an OFF cell voltage VSOF). Hence, a time t2 to take for the VRR to exceed the ON cell voltage VSON becomes longer to thereby make a read speed of an ON cell signal slower.
The conventional semiconductor memory apparatus having the read circuit has a limitation on a read speed of an ON cell signal. Thus, there is a limit in improving a performance of the semiconductor memory apparatus Itself. According to the above-mentioned consideration, this reason is as follows. That is, since the output terminal of the current detector is directly connected to the input terminal of the differential amplifier circuit, it is difficult to improve a rise performance of a detection signal applied to the input terminal. Hence, there is the limit in improving the read speed of the ON cell signal.
Therefore, an object of the present invention is to provide a semiconductor memory apparatus for improving such rise performance.
By the way, Japanese Laid Open Patent Application (JP-A-Heisei, 8-147991) discloses the following semiconductor memory apparatus. It is provided with: first and second current sensing circuits, each of which contains a first conductive type of a first MOSFET that is mounted between a first power supply voltage and its output node and has a relatively small conductance; a differential amplifier circuit in which its non-inversion and inversion input nodes are coupled to each output node of the first and second current sensing circuits and then they are selectively made active in accordance with a first inner control signal; and a sense amplifier containing second and third MOSFETs of the first conductive type, each of which is mounted parallel to the first MOSFETs constituting the first and second current sensing circuits and has a relatively large conductance and is transiently turned on immediately before the differential amplifier circuit is made active.
Japanese Laid Open Patent Application (JP-A-Heisei, 7-334998) discloses the following semiconductor memory apparatus. In the semiconductor memory apparatus provided with: a memory apparatus array for storing a data; an address buffer for capturing an address to select the data in this memory apparatus array; and a data sensing circuit for reading out a data on a selection bit line of the memory apparatus array, the data sensing circuit has: clock synchronization sense amplifiers in a plurality of systems in which input terminals are commonly connected to the selection bit line to thereby carry out a time sharing operation; and a selector for selectively outputting the data stored by those sense amplifiers. Each clock synchronization sense amplifier has: a pre-sensing circuit selectively connected to the selection bit line under the control of a synchronization clock; and a main sensing circuit for capturing and latching an output from the presensing circuit under the control of the synchronization clock.
Japanese Laid Open Patent Application (JP-A-Heisei, 8-96582) discloses the following semiconductor memory apparatus. This is a semiconductor memory apparatus for detecting a potential of a memory cell connected to a bit line from a potential of the bit line, and it is provided with: an applying unit for applying to the bit line a predetermined potential to pre-charge the memory cell; an output unit for receiving a detection signal based on the applied potential and then outputting its inversion signal as an output of the semiconductor memory apparatus; and a controller for controlling the potential to pre-charge the memory cell in accordance with the inversion signal.
Japanese Laid Open Patent Application (JP-A-Heisei, 6-325577) discloses the following semiconductor memory apparatus. That is, it is provided with: first and second bit lines; a plurality of columns composed of a plurality of memory cells designed such that first and second data input output terminals are respectively connected to those first and second bit lines, and if it is selected when a read operation is done, a current flows from any of the first and second data input output terminals in accordance with a data to be stored; first and second connection switch devices, in which they are mounted correspondingly to each of the plurality of columns, and respective first ends are connected to the first and second bit lines, and they are controlled so as to be turned on and off in accordance with a column selection signal; first and second common data lines which are mounted correspondingly to the plurality of columns, and respectively connected to second ends of the first and second connection switch devices; and a sense amplifier for detecting the current flowing through the first and second common data lines when the read operation is done, and accordingly detecting the data to be stored by the selected memory cell, the sense amplifier is designed such that when the read operation is done, a voltage of the first common data line is correlated to a voltage at a voltage detection point on the second common data line side for the sake of data detection and then a voltage of the second common data line is correlated to a voltage at a voltage detection point on the first common data line side for the sake of data detection.
Japanese Laid Open Patent Application (JP-A-Heisei, 5-266675) discloses the following semiconductor memory apparatus. In the semiconductor memory apparatus having a memory cell, a pair of bit lines, a bit selector, a pair of common data lines, a writing unit and a sense amplifier, the reading unit is provided with: a pair of transistors, each of which has a collector connected through a loading unit to a second power supply and an emitter connected to the pair of common data lines and is driven in response to the read signal; and a differential amplifier for connecting respective inputs to the collectors of the pair of transistors and then detecting a difference between the inputted mutual potentials.